Lead: Liang Liu (LU)
Co-lead: Zain-ul-Abdin,Tomas Nordström (HH)
This WP focuses on the hardware aspect of massive MIMO. In particular, the objective is to achieve energyefficient baseband processing. The research is carried out through collaboration between LU, LIU, and HH, which brings together expertise from communication theory, signal processing, and hardware implementation.
The WP is divided into 3 tasks, which together contribute to the overall goals.
– Algorithm-circuit co-design: The task will investigate low-power accelerator design for computationally
intensive functions in massive MIMO, like multi-user detection and precoding. Moreover, the overall digital baseband processor architecture will also exploited for low power, by optimizing processing distribution, memory subsystem, and on-chip data transfer networks.
– Hardware imperfections handling: The task will study how hardware imperfections affect the system
performance. This includes quantization effects, as well as errors in analog circuits like nonlinearities,
I/Q mismatches, and phase noise. The goal is to minimize the energy consumption by estimating the
precision required on the analog components and the digital computations.
– Energy-efficient parallel computing: The task is to study high-level design methodologies for baseband
processing and how massive parallelism available in manycore processor architecture can be utilized
to improve performance and energy efficiency. We also compare the usefulness of various architectural
mechanisms as evidenced by their impacts on application performance, which could guide future